电压 VDD/VDDQ | 2.5V/2.5V | 1.8V/1.8V(±0.1) | 1.5V/1.5V(±0.075) |
I/O接口 | SSTL_25 | SSTL_18 | SSTL_15 |
数据传输率(Mbps) | 200~400 | 400~800 | 800~2000 |
容量标准 | 64M~1G | 256M~4G | 512M~8G |
Memory Latency(ns) | 15~20 | 10~20 | 10~15 |
CL值 | 1.5/2/2.5/3 | 3/4/5/6 | 5/6/7/8 |
预取设计(Bit) | 2 | 4 | 8 |
逻辑Bank数量 | 2/4 | 4/8 | 8/16 |
突发长度 | 2/4/8 | 4/8 | 8 |
封装 | TSOP | FBGA | FBGA |
引脚标准 | 184Pin | 240Pin | 240Pin |